This invention relates to the manufacture of semiconductor devices with a depletable multiple-region semiconductor material that provides a voltage-sustaining space-charge zone when depleted, and to a method of fabricating such a material. The invention also relates to semiconductor material and semiconductor devices produced by such methods.
The voltage-sustaining space-charge zone results from charge-carrier depletion of interposed p-type and n-type regions that form multiple p-n junctions in the material. The intermediate dimensions (width or thickness) of the interposed p-type and n-type regions need to be small enough (in relation to their dopant concentrations) to allow depletion of the region across its intermediate dimension without the resulting electric field reaching the critical field strength at which avalanche breakdown would occur in that semiconductor. This is an extension of the famous RESURF principle. Thus, the depletable multiple-region material may be termed xe2x80x9cmultiple p-n RESURFxe2x80x9d material. In the voltage-sustaining zone formed of first regions of one conductivity type interposed with second regions of the opposite conductivity type, the dopant concentration and dimensions of the first and second regions are such that (when depleted in a high voltage mode of operation) the space charge per unit area in the first and second regions balances at least to the extent that the electric field resulting from the space charge is less than the critical field strength at which avalanche breakdown would occur in that zone.
U.S. Pat. No. 4,754,310 (our ref: PHB32740) discloses semiconductor devices with depletable multiple-region (multiple p-n junction RESURF) semiconductor material comprising alternating p-type and n-type regions which together provide a voltage-sustaining space-charge zone when depleted. The use of such material for the space-charge zone permits the achievement of a lower on-resistance in the device having a given breakdown voltage and is particularly advantageous for high voltage MOSFET devices, both lateral devices and vertical devices. Other embodiments of such devices are disclosed in U.S. Pat. No. 5,216,275, U.S. Pat. No. 5,438,215 and WO-A-97/29518. The whole contents of U.S. Pat. No. 4,754,310, U.S. Pat. No. 5,216,275, U.S. Pat. No. 5,438,215 and WO-A-97/29518 are hereby incorporated herein as reference material.
As described in U.S. Pat. No. 4,754,310, U.S. Pat. No. 5,216,275, U.S. Pat. No. 5,438,215 and WO-A-97/29518, epitaxial refill of etched trenches may be used to provide the alternating p-type and n-type regions extending perpendicular to the major surface of the device body in the case of a vertical device. However, the quality of the resulting p-n junctions and the reproducibility of the process is far from optimum.
Some alternative processes for forming the depletable multiple regions at intermediate stages in the device manufacture have been proposed. Thus, instead of epitaxial refill of etched trenches in a silicon epitaxial layer on a highly doped silicon substrate, column 5 lines 38 to 41 of U.S. Pat. No. 5,216,275 suggests selective neutron transmutation doping (NTD) to transform local zones of the n(or p) silicon layer into p(or n) regions. However, the neutrons penetrate through the epitaxial layer to the highly doped silicon substrate, and so silicon atoms and dopant atoms in the highly doped silicon substrate are also transmutated. This substrate is however required to form an active device region (drain). FIGS. 7a to 7b of WO-A-97/29518 suggest using repeated epitaxy with ion implantation of the opposite type dopant at each epitaxial stage. However this process involves many steps and so is expensive, and it is difficult to achieve the balance of the n and p dopant that is needed for RESURF with the conductivity and voltage blocking requirements of the device.
Due to the closely matched p and n type doping in cmxe2x88x922 that is needed for the multiple RESURF, it is not obvious what known processes could be advantageously used in manufacture to fabricate the multiple p-n junction RESURF semiconductor material for vertical devices.
It is an aim of the present invention to provide a low-cost yet reliable process for fabricating the multiple p-n junction RESURF semiconductor material.
According to the present invention, there is provided a method of fabricating a semiconductor wafer of a depletable multiple-region semiconductor material comprising alternating p-type and n-type regions which together provide a voltage-sustaining space-charge zone when depleted, including the steps of providing a p-type silicon body having an acceptor doping concentration corresponding to that required for the p-type regions of the material across the thickness of the body, and subjecting the silicon body to irradiation with collimated beams of thermal neutrons at window areas in a mask so as to form the n-type regions by transmutation of silicon atoms into phosphorus, whereby the phosporus dopant concentration of the resulting n-type regions extends across the thickness of the body between the opposite major surfaces of the body so that the p-n junctions formed between the alternating p-type and n-type regions terminate at the opposite major surfaces of the body.
Very good control is possible over the composition of the original p-type silicon body, whose resistivity can be precisely measured to determine its correct (low) dopant concentration level before the local neutron transmutation doping (NTD) stage. The precise neutron dose for the desired NTD concentration of phosphorus can also be accurately calibrated. By using NTD in this manner to provide a starting wafer for device manufacture, problems arising from NTD of highly doped device regions/substrates do not arise. In the subsequent device manufacture, a highly doped region/substrate may be provided at a major surface of the wafer by dopant implantation and/or diffusion or by bonding a highly doped wafer to that major surface.
The body may be of a suitable thickness to form the desired wafer for device manufacture. However, thermal neutrons have a large penetration depth in silicon. Thus, a thicker body can readily be used for the NTD. Then, after the NTD, the method may include a further step of slicing the silicon body transverse to the p-n junctions between the p-type and n-type regions so as to form the desired device wafer as a thinner body.
A wafer fabricated in accordance with the invention can be advantageously used for the manufacture of a high voltage MOSFET device having a low on-resistance. Thus, source and drain regions my be provided adjacent to respective first and second opposite major faces of the wafer, the source region being separated from the multiple p-n junctions of the space-charge zone by a channel-accommodating body region of opposite conductivity type to the drain region. A wafer of a first conductivity type may be bonded to the second major surface of the wafer of the depletable multiple-region semiconductor material, so as to provide the drain region at said second major surface.